In recent years, technical advances of image display devices has enabled the display of precise CG (Computer Graphics) images, realistic, true-to-life images with high definition, etc. Further, there has been a growing demand for the display of images with more gray scale levels and higher definition.
In a liquid crystal panel, which is a liquid crystal display device, among image display devices, a demand for display images with higher definition is also growing. In response to this demand, a liquid crystal driver LSI which is incorporated into the liquid crystal panel has been advanced for multiple outputs and multiple gray scale levels.
In the liquid crystal panel, for gray scale display, each output means of the liquid crystal driver LSI incorporates a D/A converter to output a gray scale voltage. This operation will be explained below with reference to FIG. 8. FIG. 8 is a block diagram of a typical liquid crystal driver, and particularly, a source driver section which outputs voltages for gray scale display to activate source signal lines of the liquid crystal panel.
The following description will assume that the liquid crystal driver is a source driver LSI; however, it may be a liquid crystal driver including a source driver.
Firstly, in the source driver LSI, digital input data (for example, in case of display with 64 gray scale levels, R, G, B each having 6-bit input data) corresponding to voltages for gray scale display which are outputted to the respective source signal lines of the liquid crystal panel are subjected to sequential sampling in a sampling memory in accordance with a start pulse signal (not shown) transferred from a shift register by a transfer clock CK, and data for one horizontal synchronization period (simultaneously, data for the number of outputs) are picked up and temporarily latched in a hold memory.
Next, the digital input data and the data for one horizontal synchronization period are outputted at the same time by a horizontal synchronizing signal LS, and the digital input data is risen its voltage to the level of a voltage applied to the liquid crystal panel via a level shifter to be transferred to the D/A converter. This D/A converter is placed with each output (e.g. 540 output terminals) of the source driver.
Subsequently, in the DA converter, the voltage for gray scale display, corresponding to the above digital input data whose voltage has been risen, is selected, and the voltage for gray scale display is outputted via an output operational amplifier which is placed with each output and inputted to each source signal line of the liquid crystal panel.
Note that, the voltage for gray scale display (e.g. voltage for 64-levels of gray scale display) is generated in a reference voltage generating circuit (ladder resistor) in accordance with a reference voltage (e.g. V0, V1, . . . , V10, . . . ) inputted from an outside source, and outputted to the D/A converter.
As the above reference voltage generating circuit generally used is a ladder resistor. The ladder resistor will be explained with reference to FIG. 6. FIG. 6 is a schematic diagram of a typical ladder resistor.
In FIG. 6, the ladder resistor has terminals V0 to Vn to input reference voltages from outside of the LSI, and each voltage for n+1-levels of gray scale display is outputted from the two ends of ladder resistors m1 to mn to the D/A converter circuit. In FIG. 6, arrows to the D/A converter circuit is omitted.
Note that, an example of the terminals V0-Vn is given in FIG. 6; however, this is only an example of the terminals.
Thus, the change of a reference voltage value enables a correction in accordance with γ characteristic as described later.
In the reference voltage generating circuit shown in FIG. 8, in the case where the foregoing input display data are 6 bits, 8 bits, and 10 bits, voltages for n=64, 256, 1024 levels of gray scale display are generated, respectively.
Further, with the advance for multiple gray scale levels of the liquid crystal driver LSI, acceptable limits of variation of each voltage for gray scale display are held small, so that a highly accurate measurement is essential for a test of a liquid crystal driver securing this quality. Specifically, it is necessary to carry out a higher accurate test to determine whether all of the voltages for gray scale display, which are outputted from the respective D/A converters of the source driver LSI, are at a proper level within acceptable limits and whether the outputted gray scale voltage values are uniform one another among the D/A converters, each of which is placed with the output terminal.
Under the condition where a power supply voltage of a device under test DUT (Device Under Test) is the same, the improvement in the performance of output terminals from 64-levels of gray scale display to 256-levels of gray scale display requires four-fold accuracy in the measurement.
Referring to FIG. 9, the following will explain a testing method using a liquid crystal driver LSI (source driver LSI) which incorporates m-number of output terminals and n-level gray scale D/A converters to output voltages by selecting from n-number of voltage levels (voltage for gray scale display), as a device under test DUT which is a target device for a test.
FIG. 9 is an example of testing a liquid crystal driver LSI 111 as a device under test DUT (hereinafter, referred simply to as DUT), using a semiconductor testing device (tester) 112.
The tester 112 inputs input signal corresponding to predetermined display data to the DUT 111 and judges whether the output signal outputted from the DUT 11 is at a proper level.
The test system in FIG. 9 causes the DUT 111, i.e. liquid crystal driver LSI to input an input signal (predetermined display data) from RGB input terminals using the tester 112 (In FIG. 9, only the D/A converters (DAC) are described among the components in FIG. 8, and output operational amplifiers and others are omitted.), and to output voltages for gray scale display in accordance with the display data.
First, for example, the lowest voltages for gray scale display outputted from output terminals Y1-Ym of the DAC are inputted by time division to the respective matrix switches whose open/close operation is sequentially controlled in the tester 112. Then, the outputs from the terminals Y1 to Ym are sequentially measured as voltages for 1st level gray scale display by a highly precise analog voltage measuring device 115 included in the tester 112. The measurement results are sequentially stored in a data memory 113 included in the tester 112.
By repeating this operation for n-levels of gray scale, data for all levels of gray scale by all output terminals (m×n-number of data) are stored in the data memory 113.
Data stored in the data memory 113 are subject to a predetermined operation using an operating device 114 which is included in the tester 112 to carry out a uniformity test for determining whether each value of the gray scale voltage for the output terminal and the values of gray scale voltages among the output terminals fall within acceptable limits.
In such a test for a liquid crystal driver LSI (source driver LSI), with the advance of multiple outputs and multiple gray scale levels, the increase in volume of picked-up data increases a data processing time, resulting in a drastic increase in test time.
Japanese Unexamined Patent Publication (Tokukai 2001-99899; published on Apr. 13, 2001) discloses a test system which solves the problem of the increase in test time in the foregoing test system shown in FIG. 9.
A technique adopted in the test system for solving the problem of the increase in test time is that differential voltages between an ideal voltage for each gray scale level and voltages outputted from the respective output terminals found by a differential amplifier array module provided corresponding to each of the output terminals, are determined in parallel using a comparator inside the tester so that an equivalent test to the conventional test is carried out in a short time.
The test system will be explained below with reference to FIG. 10. In FIG. 10, a DUT 121 as a device under test is tested by a tester 122, a voltage generator 123, and a differential amplifier array module 124. Note that, as to the DUT 121 and tester 122, detailed explanations are omitted here because they are the same as the DUT 111 and tester 112.
The voltage generator 123 generates an expected voltage level to be outputted by the DUT 121, i.e. an ideal output voltage. The differential amplifier array module 124 amplifies differential voltages between output signals from the voltage generator 123 and output signals from the output terminals of the DUT 121 and outputs the amplified output voltages to the tester 122. Here, the following will also explain an example of testing method using a liquid crystal driver LSI (source driver LSI) which incorporates m-number of output terminals (Y1 to Ym) and n-level gray scale D/A converters to output voltages by selecting from n-number of voltage levels, as a device under test DUT 121 which is a target device for a test. The
The DUT 121 includes m-number of output terminals each of which has a D/A converter (DAC), and as described previously, generates voltages for n-levels of gray scale display in accordance with to the display data. Note that, in FIG. 10, in the DUT 121, output operational amplifiers and others are omitted as in the case of the DUT 111.
First, an input signal corresponding to display data is given from the tester 122 to the DUT 121, and the DUT 121 is caused to operate so as to generate, for example, the same voltages for gray scale display from the m-number of output terminals.
The voltages for gray scale display outputted from the m-number of output terminals are respectively inputted at once (in parallel) to input terminals of differential amplifiers included in the differential amplifier array module 124.
Meanwhile, simultaneously with the input of the gray scale voltages from the respective output terminals of the DUT 121, a value as an expected value voltage for the voltage for gray scale display is outputted from the voltage generator 123 and inputted to another input terminal of an differential amplifier included in the differential amplifier array module 124.
Differential voltages between m-number of voltages for gray scale display outputted from the DUT 121 and the expected value voltage generated in the voltage generator 123, i.e. shift amount from the expected value voltage are amplified by the differential amplifiers. The amplification by the differential amplifiers is carried out for the realization of a highly precise comparative determination of the differential voltages.
The m-number of amplified voltages are outputted respectively from the output terminals of the differential amplifier array module 124 and inputted in parallel to tester channels (1 ch to Mch) of the tester 122.
The tester 122 includes a DC measurement unit for the measurement of DC voltage level with high accuracy and the comparator provided to the foregoing tester channels as means for measuring voltages. The comparator, which is a device for carrying out a functioning test, is less accurate in voltage measurement than the DC measurement unit. Therefore, the comparator usually cannot carry out the highly accurate voltage measurement and comparative determination as described above; however, the amplification of the differential voltages by the foregoing amplifying means allows the comparative determination by the comparator.
Thus, the measurement using the differential amplifier array module 124 realizes a short-time test that is equal in measurement accuracy to or better than the conventional test.
FIG. 7 shows a relation in waveform between the expected value voltage from the voltage generator 123 and the output voltage from the DUT 121 (hereinafter, referred to as gray scale voltage) both of which are inputted to the differential amplifier array module 124.
The gray scale voltage outputted from the DUT 121 causes shift voltages ΔV1, ΔV2, ΔV3 . . . with respect to the expected value voltage. The test for the DUT 121 determines whether these shift voltages ΔV fall within a predetermined voltage range and determined whether these shift voltages ΔV have a uniformity by comparison of the voltages between the output terminals with respect to the same level of gray scale.
Further, in the test system disclosed in the above publication, each expected value voltage for the voltages for every level of gray scale display is outputted from the expected value voltage generator 123. As this expected value voltage, an expected value voltage which is preset in the form reflecting the later-described γ characteristic specifications and others is operated separately in accordance with an input signal inside a test program in operating means (incorporated in the tester 122), and the operation result is transferred to the expected value voltage generator 123 to output the expected value voltage reflecting the γ characteristic.
However, in recent years, with the increase in number of gray scale level, exacting specifications have been provided to a shift voltage ΔV between an ideal output voltage, i.e. expected value voltage for a device under test DUT as liquid crystal driver and an actual output voltage, i.e. gray scale voltage from the liquid crystal driver. Generally, the shift voltage ΔV is defined to be within ±20 mV for specifications of 64-level gray scale and within ±10 mV for specifications of 256-level gray scale. Decrease to ±several mV with further increase in number of gray scale level is a matter of hours.
Further, since the expected value voltage is operated in accordance with the formula preset by γ characteristic specifications and others inside a test program and the operation result is transferred to the voltage generator to output as expected value voltage, a time for the transfer of this operation result data has increased with the increase in the number of gray scale levels.
Specifically, when the output voltage in accordance with the γ characteristic, which is produced by operation inside the test program, is transferred from the tester to the voltage generator, in some cases, the data must be transferred serially with 1 ch for limitation of the number of I/O channels in the tester.
In this case, for example, a dot inverse-capable liquid crystal driver LSI (source driver LSI) for 256-level gray scale display, in which adjoining terminals are activated with alternating current by each pixel (dot) of a liquid crystal panel, requires positive and negative data. Therefore, data for 512-level gray scale display must be transferred.
When 3 minutes is required for the transfer of one data (6 bits or more is necessary for the test of a liquid crystal driver for 64-level gray scale display), 1.5 seconds is required only for the transfer of the expected value voltage.
The number of bits for this transferred data is connected with the measurement accuracy that comes from the accuracy of the reference voltage generator itself. For example, in order to determine ±20 mV, which is a general specification for output variation, a tester needs to be more than tenfold more accurate than a device which determines ±20 mV.
To secure tenfold or more measurement accuracy, it is necessary to increase the accuracy by further 3 bits with respect to 6 bits of display data. As a result, 9 bits (6+3 bits) of transferred data is necessary.
Further, the increase in the number of gray scale levels proportionally accelerate the improvement in measurement accuracy, and how to realize a highly accurate measurement is one of the important problems. Therefore, the improvement in measurement accuracy further increases the number of bits for transferred data, resulting in the increase in time for data transfer.
Actually, when a determination time of the shift voltage is compared with a transfer time of the expected value voltage, the ratio of the determination time and the transfer time is 1:2 to 1:3. The necessity of the improvement in measurement accuracy with the increase in the number of gray scale levels further increases the ratio.
As a result, a time that is not virtually necessary for a test (setting time, etc) becomes longer. This results in the increase in test time, i.e. degradation of test performance.